clock design meaning in Chinese

时钟位置

The improved design of fifo in respect of multi - asynchronous clock designs acquires perfect working performance
从异步多时钟系统设计角度提出的fifo的改进方案获得了良好的工作效果。
Those include power supply circuit design ; ground plane design and sample clock design . combining some radar development , its high - speed a / d circuit is tested , and has given out some test results
最后结合某雷达研制，对其高速模数转换电路设计进行了实际测试评估，并给出了部分测试结果。
The paper compares some algorithms on rs decoding , makes improvements based on the me algorithm , removes the modifying step in decoding truncate rs code , corrects unsuitable statements in the related papers , and parameterizes the rs decoding module , reducing its area by 20 % . the paper overcomes the signal integration problem in multi - clock design , greatly lowers the phase jitter without area increase , introduces pll to adjust rate for the first time , and parameterizes the module
本文比较了实现rs解码的几种算法，并在me算法基础上进行改进，创造性的去掉了缩短码解码中的校正环节，纠正了有关论文中的不当论述，并将rs解码模块进行了参数化设计，同时也将rs解码的规模缩小了20 ；克服了多时钟设计中的信号完整性难题，在没有增加模块面积的条件下，大幅降低数据的相位摘要抖动，首次引入锁相环来调整速率。